1. Field of the Invention
The present invention generally relates to a display device and, more particularly, to a liquid crystal display device and a fabricating method thereof.
2. Description of the Related Art
Generally, liquid crystal display (LCD) devices control light transmissivity of liquid crystal cells in response to video signals to display an image. Active matrix LCDs having a switching device for each liquid crystal cell is suitable for displaying moving pictures. In active matrix LCDs, thin film transistors (TFT) are typically used as the switching device. For example, an LCD may include thin film transistors (TFTs) provided at each intersection between gate lines and data lines, a lower substrate including pixel electrodes connected to TFTs, an upper substrate including color filters, and liquid crystals injected between the upper and lower substrates. The TFT comprises a gate electrode, a gate insulating film, an active layer, and source and drain electrodes and switch a data signal from the data line to the pixel electrode in response to a gate signal received from the gate line to drive the liquid crystal cell.
FIGS. 1A to 1E show a method of fabricating a lower substrate of a conventional LCD and, in particular, a TFT and a gate pad portion.
In FIG. 1A, a gate metal layer is deposited onto a transparent substrate 10 to have a thickness of about 2000Δ by a sputtering process, for example. A high conductivity aluminum alloy such as aluminum-neodenium (AlNd) is usually used as the gate metal layer. Subsequently, the gate metal layer is patterned by photolithographic and wet etching processes to form gate patterns including a gate electrode 12 and a gate pad 14.
In FIG. 1B, a gate insulating film 16 is formed entirely upon the transparent substrate 10 including the gate patterns. The gate insulating film 16 may be made of silicon oxide (SiOx) or silicon nitride (SiNx), for example. A semiconductor layer and a semiconductor layer doped with an impurity are sequentually deposited upon the gate insulating film 16 by a chemical vapor deposition (CVD) process, for example. Then, the semiconductor layer and the semiconductor layer doped with an impurity are patterned by photolithographic and dry etching processes to form an active layer 18 and an ohmic contact layer 20.
In FIG. 1C, a source/drain metal material is deposited upon the gate insulating film 16 including the active layer 18 and the ohmic contact layer 20 by a sputtering process, for example. The source/drain metal material includes chrome (Cr), molybdenum (Mo), titanium (Ti) or tantalum (Ta), or a molybdenum alloy such as molybdenum-tungsten (MoW), molybdenum-tantalum (MoTa) or molybdenum-niobium (MoNb). The source/drain metal layer is patterned by photolithographic and wet etching processes to form source/drain patterns that include a data line (not shown), a data pad (not shown), a source electrode 22, and a drain electrode 24. Then, a portion of the ohmic contact layer 20 that is exposed between the source electrode 22 and the drain electrode 24 is removed by a dry etching process to electrically separate the source electrode 22 from the drain electrode 24.
In FIG. 1D, a passivation layer 26 is formed upon the gate insulating film 16 including the source/drain patterns. The passivation layer 26 is made of an organic material such as silicon nitride or silicon oxide, for example, or an inorganic material such as an acrylic organic compound, BCB (benzocyclobutene), PFCB (perfluorocyclobutane), for example. The passivation layer 26 is patterned by photolithographic and dry etching processes to form a contact hole exposing a portion of the drain electrode 24 and to form a contact hole exposing a portion of the gate pad 14 and a data pad (not shown).
In FIG. 1E, a transparent electrode layer is formed upon the passivation layer 26 by a deposition technique such as sputtering, for example. The transparent electrode layer is made from indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), for example. Then, the transparent layer is patterned by photolithographic and etching processes to form a pixel electrode 28 and a protective electrode 30. The pixel electrode 28 is electrically connected to the drain electrode via the contact hole previously formed in the passivation layer 26. The protective electrode 30 is connected to the gate pad 14 via the contact hole previously formed in the passivation layer 26.
In such a conventional LCD device, an aluminum alloy material with high electrical conductivity is generally used as a material for forming the gate metal electrode. Since unalloyed aluminum has problems associated with hillock formation and diffusion into adjoining materials, an aluminum alloy such as AlNd, for example, has been used. However, such an aluminum alloy metal creates a large electrical contact resistance between the pixel electrode and the transparent electrode. Accordingly, the gate metal electrode utilizes a double metal layer structure including material combinations such as Mo/AlNd, Mo/Al or Cr/AlNd containing Mo or Cr, for example, which has improved electrical contact resistance with respect to materials used for forming the transparent electrode.
FIGS. 2A to 2E show a method of fabricating a lower substrate of an LCD employing a double gate metal layer.
In FIG. 2A, a first gate metal layer of an aluminum alloy metal is deposited entirely upon the transparent substrate 10 and then patterned to form a first gate pattern 31. Then, a second gate metal layer of an improved electrical contact resistance material such as Mo or Cr, for example, is deposited entirely upon the first gate pattern 31 and then patterned to form a second gate pattern 33. Accordingly, the gate electrode 34 and the gate pad 36 are formed to both include the first gate pattern 31 and the second gate pattern 33.
In FIG. 2B, the gate insulating film 16 is formed entirely upon the transparent substrate 10 including the gate electrode 34 and the gate pad 36. A semiconductor layer and a semiconductor layer doped with an impurity are sequentually deposited onto the gate insulating film 16 and then patterned to form the active layer 18 and the ohmic contact layer 20.
In FIG. 2C, a source/drain metal layer is deposited entirely upon the gate insulating film 16 including the active layer 18 and the ohmic contact layer 20 and then patterned to form source/drain patterns that includes the data line (not shown), the data pad (not shown), the source electrode 22, and the drain electrode 24. Then, a portion of the ohmic contact layer 20 that is exposed between the source electrode 22 and the drain electrode 24 is removed by a dry etching process to electrically separate the drain electrode 24 from the source electrode 22.
In FIG. 2D, the passivation layer 26 is deposited entirely on the gate insulating film 16 and the source/drain patterns. The passivation layer is then patterned to form a contact hole for exposing a portion of the drain electrode 24 and to form a contact hole exposing portions of the gate pad 36 and the data pad (not shown).
In FIG. 2E, a transparent electrode layer is deposited entirely upon the passivation layer 26 and then patterned to form the pixel electrode 28 and the protective electrode 30. The pixel electrode 28 is connected to the drain electrode via the contact hole previously formed in the passivation layer 26. The protective electrode 30 is electrically connected to the gate pad 36 via the contact hole previously formed in the passivation layer 26 and the gate insulating film 16.
As described above, the gate metal layer includes the first gate metal layer formed of an aluminum-alloy metal and the second gate metal layer that provides an improved electrical contact resistance, thereby reducing an electrical contact resistance between the gate pad 36 and the transparent electrode 30. However, two masking processes are required to form the gate metal into a double metal layer structure. The masking processes generally include a plurality of processes such as deposition, cleaning, photoresist coating, exposure, development, etching, photoresist stripping and inspection. Therefore, using a two mask process to form the gate electrode and the gate pad with a double layer structure is problematic since the large number of additional processes can create a bad process ratio and increase manufacturing costs.